Field of the Invention
The present invention relates to a metal oxide semiconductor (MOS) field effect transistor configuration in which the body region of a MOS transistor is connected to a semiconductor body and via the latter is at a fixed potential.
Attempts have been made for a long time to implement MOS field effect transistor configurations that have a small area, low capacitances and, are able to carry high currents. MOS field effect transistor configurations which meet these requirements to a large extent are implemented in silicon-on-insulator (SOI) technology, as is known (in this regard, see for example the reference by Stephen C. Kxc3xchne at al., titled xe2x80x9cSOI MOSFET with Buried Body Strap by Wafer Bondingxe2x80x9d in IEEE Transactions on Electron Devices, volume 45, no. 5, May 1998, pages 1084 to 1090). In such MOS field effect transistor configurations using SOI technology, however, the body region is to be at a fixed potential, in order that no xe2x80x9ckink effectsxe2x80x9d, that is to say bends and discontinuities in the current/voltage characteristic, occur. However, in MOS field effect transistor configurations in SOI technology it has not hitherto been possible to keep the body region at a fixed potential, since the region adjoins the insulator, so that hitherto it has not appeared to be possible without great effort to supply the body region with a fixed potential.
It is accordingly an object of the invention to provide a MOS field effect transistor configuration that overcomes the above-mentioned disadvantages of the prior art devices and methods of this general type, which uses a technology similar to SOI technology but in which the body region can readily be kept at a fixed potential.
With the foregoing and other objects in view there is provided, in accordance with the invention, a metal oxide semiconductor (MOS) field effect transistor configuration. The configuration contains a semiconductor body and a semiconductor pillar pointing away from the semiconductor body and forming a body region. The body region is connected to the semiconductor body and due to the semiconductor body, the body region is at a fixed potential. A filling insulator surrounds the semiconductor pillar and is disposed on the semiconductor body. A source, a drain and a gate are embedded between the semiconductor pillar and the filling insulator.
In a MOS field effect transistor configuration of the type mentioned at the beginning, according to the invention, the object is achieved by the source, drain and gate of the MOS transistor being embedded between a semiconductor pillar which points away from the semiconductor body and forms the body region and a filling insulator which surrounds the semiconductor pillar and is situated on the semiconductor body.
The MOS field effect transistor configuration according to the invention has a xe2x80x9cside-wall transistor structurexe2x80x9d: a semiconductor pillar made, for example, of p-conductive silicon is situated on the surface of a semiconductor body, which can likewise consist of p-conducting silicon, and is embedded there on the surface in a filling insulator, such as silicon dioxide or another suitable insulator (silicon nitride or silicon dioxide and silicon nitride and so on).
Of course, another suitable semiconductor material can be selected instead of silicon, such as an AIIIBV composite semiconductor or SiC and so on. It is likewise possible to provide a semiconductor body and a semiconductor pillar of the n-conductivity type instead of the p-conduction type.
Parallel to the semiconductor pillar, into the boundary region between the semiconductor pillar and the filling isolator surrounding the latter, trenches for the source and drain are driven in and, in the case of a p-conducting semiconductor pillar, are filled with n+-conducting polycrystalline silicon, so that n-conducting zones for source and drain are produced in the semiconductor pillar itself as a result of diffusion.
Situated between the trenches for the source and drain is a gate trench, whose walls and bottom are covered with an insulating layer of silicon dioxide and/or silicon nitride, for example, and which is otherwise filled, like the source and drain trenches, with n+-conducting polycrystalline silicon. Here, the gate trench can be provided in such a way that it touches or else intersects the trenches for source and/or drain.
In such a configuration, the channel of the field effect transistor is formed by the sidewall of the semiconductor pillar. A depth of the gate, source and drain trenches determines the channel width, while the channel length is determined by the distance between the source and drain on the sidewall of the semiconductor pillar along the gate trench.
With the MOS field effect transistor configuration according to the invention, it is possible to implement large relationships between a channel width W and a channel length L on a very small area, that is to say to achieve large values for W/L and to have small capacitances for the conductors.
It is of great importance that, in the MOS field effect transistor configuration according to the invention, the body region that is formed by the semiconductor pillar can readily be at a fixed potential via the semiconductor body that is connected to the body region.
The invention advantageously permits the production of n-channel and p-channel field effect transistors. The semiconductor pillar can therefore have the n-conductivity type and the p-conductivity type in the same way. The n-channel and p-channel field effect transistors can readily be supplied with a suitable body voltage via the associated p-conducting and n-conducting semiconductor bodies.
In a development of the invention, it is possible to implement semiconductor pillars of various conductivity types for at least one n-channel MOS field effect transistor on a semiconductor body and to implement a p-channel MOS field effect transistor in a CMOS configuration. For this purpose, it is merely necessary for the xe2x80x9csubstrate zonexe2x80x9d forming the semiconductor body for the n-channel MOS field effect transistor to be p-dopedxe2x80x94as explained at the beginningxe2x80x94while n-doping is provided for the substrate zone of a p-channel MOS field effect transistor.
The source, drain and gate electrodes of polycrystalline silicon in the MOS field effect transistor configuration according to the invention can readily be wired in a three-layer connection system if suitable contact holes are provided between the individual levels of the polycrystalline silicon. These levels can readily be wired in a multi-layer metallization.
Suitable filling insulators are materials with a low dielectric constant or a combination of such materials, such as silicon dioxide, undoped polycrystalline silicon and so on.
In a process for the production of the MOS field effect transistor configuration according to the invention, first a pxe2x88x92 (or nxe2x88x92) conducting semiconductor pillar is etched on a surface of a semiconductor body. The semiconductor body has the same conductivity type as the semiconductor pillar. A filling insulator of silicon dioxide, for example, is then applied around the pillar. In the boundary region between the filling insulator and the initial semiconductor pillar, a trench for the source is then introduced by isotropic etching. The trench is provided with a filling of n+-conducting polycrystalline silicon. Following structuring and intermediate insulation, the trench for the drain is etched and provided with a filling of n+-conducting polycrystalline silicon. There then follows the etching for the drain level. Following a further intermediate insulation, the trench for gate is etched and the gate insulating layer is produced. Then, a filling of n+-conducting polycrystalline silicon for the gate level is introduced into the trench and is subsequently structured. There finally follows a multilayer metallization for the source, drain and gate.
With the invention, it is possible to produce MOS field effect transistors with an L/W ratio of about 0.1 xcexcm/5 xcexcm, the area requirement corresponding to a conventional lateral field effect transistor with a corresponding L/W ratio of 0.1/1.
MOS field effect transistors according to the present invention are suitable in particular for logic ICs and for low-voltage CMOS ICs with a high operating speed, such as are used in particular in telecommunications or in portable computers.
It should also be noted that the cross section of the initial semiconductor pillar before the etching of the trenches for the source, drain and gate does not necessarily need to be rectangular but can also assume other shapes. Specifically, for example, it can be an oval, T-shaped or else trapezoidal.
With the foregoing and other objects in view there is provided, in accordance with the invention, a process for producing a metal oxide semiconductor (MOS) field effect transistor configuration. The method includes providing a semiconductor body, etching an initial semiconductor pillar in the semiconductor body, surrounding the initial semiconductor pillar with a filling insulator, and forming trenches for a source, a drain and a gate in a boundary region between the initial semiconductor pillar and the filling insulator, so that, of the initial semiconductor pillar, only a semiconductor pillar forming a body region remains. A dopant of a first conductivity type opposite to a dopant of a second conductivity type of the semiconductor pillar is introduced from the trenches for the source and the drain into regions of the semiconductor pillar which adjoin the trenches. A trench of the trenches is filled with an insulating layer, and a conductive material is disposed on the insulating layer for forming the gate.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a MOS field effect transistor configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.